Assignment 03: Context Switching and CPU Dispatch

Self-Assessment

Topic 1: Context Switching Fundamentals & The PCB

Exercise 1.1: The Mechanism of State Transfer Describe the three precise phases involved in the CPU hand-off during a context switch. Identify the specific data structure utilized during this operation and list three critical pieces of CPU state stored within it.

Exercise 1.2 (Advanced): Memory Protection and Kernel Isolation During a context switch, system call, or hardware interrupt, the operating system kernel relies on its own stack for execution rather than using the active user process’s stack. Based on the fundamental differences between User Mode and Kernel Mode, explain why this isolation is architecturally necessary.

Topic 2: The Dispatcher & Scheduling Cycle

Exercise 2.1: Delineating OS Components The CPU Scheduler and the Dispatcher operate sequentially but serve entirely different functions in the Process Scheduling Cycle. Clearly distinguish the roles of both components. What are the three specific responsibilities of the Dispatcher?

Exercise 2.2 (Advanced): Thread vs. Process Context Switching Context switching introduces direct overhead (CPU cycles). Explain why a context switch between two threads belonging to the same process is generally faster than a context switch between two entirely different processes. Identify the specific type of indirect overhead that is avoided during a thread-to-thread switch.

Topic 3: Execution Modes & The Scheduler Paradox

Exercise 3.1: Resolving the Scheduler Paradox A common misconception is that the OS Scheduler is a process that must wait in a queue for its turn on the CPU. Explain why the scheduler is NOT a scheduled process. How does the kernel actually gain control of the CPU to execute scheduling decisions?

Exercise 3.2 (Advanced): The DMA and Interrupt Lifecycle Direct Memory Access (DMA) allows devices to transfer data without constant CPU involvement. Trace the exact sequence of hardware and software events—including mode switches, queue transitions, and interrupts—that occur when a user process issues a read() system call that is handed off to a DMA controller, up to the point where the process is ready to run again.

Topic 4: Performance, Overhead, and Thrashing

Exercise 4.1: Quantifying Dispatch Latency An operating system runs on hardware with a direct context switch overhead of 8 microseconds.

1. If the CPU scheduler allocates a time slice (quantum) of 4 milliseconds to each process, what percentage of the CPU’s time is consumed purely by context switching overhead?
2. If the OS designers reduce the time slice to 500 microseconds to improve interactive responsiveness, what is the new percentage of overhead? What trade-off does this illustrate?

Exercise 4.2 (Advanced): The Collapse of Performance System administrators note that an application server is exhibiting extremely low CPU utilization while the hard drive is constantly reading and writing. Identify this phenomenon. Explain the precise relationship between an excessively high degree of multiprogramming, Cache/TLB pollution, and the onset of this systemic failure.